Packaging structure and fabricating method thereof

ABSTRACT

A packaging structure including an interposer structure, a first electronic component, and a second electronic component is provided. The interposer structure includes a first dielectric layer, a plurality of contacts, a capacitive element, and an interconnection. The contacts are disposed on the upper and lower surfaces of the first dielectric layer and the capacitive element, which comprises two conductive layers and a second dielectric layer located among the layers, is embedded into the first dielectric layer. And the interconnection is embedded into the first dielectric layer, while the capacitive element electrically connects to the corresponding contacts through the interconnection. The first and the second electronic components are disposed respectively on the upper and bottom sides of the interposer structure and electrically connected to the corresponding contacts.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 95133410, filed Sep. 11, 2006. All disclosure of the Taiwanapplication is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and amanufacturing method thereof. More particularly, the present inventionrelates to a packaging structure and a manufacturing method thereof.

2. Description of Related Art

The technology of stacking chips can shorten the transmission pathway ofelectronic signals and provide an efficient technique to integratedifferent material chips. In terms of the latter, it can stack up thehigh-frequency power amplifier chips and radio frequency chips, or canbe integrated with the micro-electro mechanical system devices.Moreover, the overall performance of the stacked-chip packagingstructure can be improved if the passive elements can be integratedeffectively. Therefore, it is essential to provide a high quality andhighly integrated interposer structure with passive elements between thestacked chips.

Referring to FIG. 1, it is a schematic view of a conventional stackedcircuit device. The conventional stacked circuit device 100 is disclosedin U.S. Pat. No. 6,661,088, wherein it includes a chip 110, aninterposer structure 120 and a substrate 130. A plurality of pads 112disposed on the chip 110 is electrically connected to the correspondingmultiple pads 132 disposed on the substrate 130 through the interposerstructure 120. The main purpose of the interposer structure 120 is toserve as circuit redistribution.

Another conventional stacked circuit device is provided for the purposeof integrating different type circuit elements such as active elementsand passive elements to the interposer structure. Referring to FIG. 2,it is a schematic view of another conventional stacked circuit device.The conventional stacked circuit device 200 disclosed in U.S. Pat. No.6,614,106 includes a chip 210, an interposer structure 220 and a basesubstrate 230. It should be noted that for the sake of clarifieddescription, FIG. 2 also shows the enlarged view of the interposerstructure 220. A plurality of terminals 212 of the chip 210 areelectrically connected to the corresponding multiple terminals 222 ofthe interposer structure 220. Whereas the other terminals 224 of theinterposer structure 220 are electrically connected to the set ofterminals of the base substrate 230. The interposer structure 220comprises an insulating film 226, a semiconductor substrate 228, and aplurality of circuit elements 229 such as the active and passiveelements which are disposed in the insulating film 222.

Other related techniques of fabricating passive elements on thesemiconductor base material of the interposer structure are disclosed inU.S. Pat. Nos. 6,500,724, 6,819,001 and 6,274,937. However, fabricatingpassive elements on the semiconductor base material may leads to lowquality factor of inductive elements, inferior capacitance due to thelimitations of material and processing temperature of semiconductor, andpoor resistance of the resistive elements.

To overcome the aforementioned drawbacks, the method of fabricatingpassive elements on the insulating materials, ceramic or plastic, of theinterposer structure are proposed and the related techniques aredescribed in the U.S. Pat. Nos. 6,933,601, 6,611,419 and 5,530,288.However, it often cost more since to fabricate inductive elements onceramic base substrate, the higher priced material, silver, is oftenused. On the other hand, the quality factor of the inductive elements isdecreased while adopting epoxy resin as the dielectric material tofabricate the inductive element on a plastic substrate. In addition, itmay cause poor capacitance when fabricating capacitive elements on theinsulating substrate, less process compatibility when manufacturingresistive elements on the ceramic substrate, and unstable resistancewhen forming the resistive elements on the plastic substrate. Also, itmay cause the final product of the interposer structure bigger andthicker when fabricating passive elements on the insulating basematerials.

SUMMARY OF THE INVENTION

The present invention provides a packaging structure, wherein theinterposer structure has better quality passive elements and is in athinner and smaller size.

The present invention also provides a manufacturing method of thepackaging structure, which is compatible with the conventionalfabricating process and has lower cost.

As embodied and broadly described herein, the present invention isdirected to a packaging structure, which includes an interposerstructure, a first electronic component and a second electroniccomponent. The interposer structure includes a first dielectric layer, aplurality of contacts, a capacitive element and an interconnection. Thecontacts are disposed on the upper and lower surfaces of the firstdielectric layer and the capacitive element, which comprises twoconductive layers and a second dielectric layer among them, is embeddedinto the first dielectric layer. The interconnection is embedded intothe first dielectric layer and the capacitive element electricallyconnects to the corresponding contacts through the interconnection. Thefirst electronic component and the second electronic component areelectrically connected to the contacts and respectively disposed on theupper and lower sides of the interposer structure.

According to an embodiment of the present invention, the permittivity ofthe aforementioned first dielectric layer is smaller than that of thesecond dielectric layer.

According to an embodiment of the present invention, the packagingstructure further comprises an inductive element embedded into the firstdielectric layer. Further, the inductive element may be disposedsurrounding the capacitive element.

According to an embodiment of the present invention, the capacitiveelement further includes a barrier layer, which is disposed between oneof the conductive layers and the second dielectric layer. In addition,the material of the barrier layer may be titanium (Ti), platinum (Pt),or silver (Ag).

According to an embodiment of the present invention, the material of thesecond dielectric layer includes ceramic, such as barium titanate(BaTiO3) or strontium titanate (SrTiO3).

According to an embodiment of the present invention, the material of thefirst dielectric layer includes benzocyclobutene (BCB) or polyimide(PI).

According to an embodiment of the present invention, the interposerstructure further includes a resistive module, which is embedded intothe first dielectric layer and stacked up with the capacitive element,and the resistive module is electrically connected to the correspondingcontacts through the interconnection.

According to an embodiment of the present invention, the resistivemodule comprises a substrate and a resistive thin film disposed on thesubstrate and electrically connects to the interconnection. In addition,the resistive module may further comprise a plurality of electrodes,which are disposed on the substrate and the resistive thin film isconnected to the interconnection through the electrodes; and apassivation layer, which is disposed on the substrate and covers theresistive thin film and the electrodes. Furthermore, the material of thesubstrate may be ceramic.

According to an embodiment of the present invention, the firstelectronic component is a semiconductor chip or a wafer.

According to an embodiment of the present invention, the secondelectronic component is a semiconductor chip or a wafer.

The present invention is also directed to a fabricating method ofpackaging structure, which comprises: forming a capacitive element;forming a first dielectric layer on a first electronic component byperforming a build-up process, forming an interconnection in the firstdielectric layer, and forming a plurality of contacts on the upper andlower surfaces of the first dielectric layer, wherein the capacitiveelement is embedded in the first dielectric layer during the fabricationof the interconnection and the capacitive element is electricallyconnected to the corresponding contacts through the interconnection;and, disposing a second electronic component on the first dielectriclayer, wherein the second electronic component is electrically connectedto the corresponding contacts.

According to an embodiment of the present invention, the capacitiveelement comprises two conductive layers and a second dielectric layerlocated among them, in which the permittivity of the first dielectriclayer is smaller than that of the second dielectric layer.

According to an embodiment of the present invention, the fabricatingmethod of the packaging structure further comprises forming an inductiveelement at the same time of fabricating the interconnection and theinductive element is electrically connected to the correspondingcontacts through the interconnection. Further, the inductive element maybe disposed surrounding the capacitive element.

According to an embodiment of the present invention, the steps offorming the capacitive element includes: providing a metal film; coatinga dielectric material on the metal film; and, forming an electrode layeron the dielectric material. The dielectric material includes, forexample, ceramic slurry.

In addition, the fabricating method of the packaging structure mayfurther comprise performing a thermal treatment process to thedielectric material after coating the same.

The fabricating method of the packaging structure may further compriseforming a barrier layer on the metal film before coating the dielectricmaterial.

According to an embodiment of the present invention, the finishedcapacitive element is trimmed into a certain size after the electrodelayer is formed.

According to an embodiment of the present invention, the fabricatingmethod of the packaging structure may further comprise performing anetching process to the capacitive element to define the surface areathereof after the capacitive element is embedded into the firstdielectric layer.

According to an embodiment of the present invention, the fabricatingmethod of the packaging structure further comprises providing aresistive module at the same time of fabricating the interconnection,and making the resistive module and the capacitive element stacked upwith each other and to be embedded into the first dielectric layer,wherein the resistive module is electrically connected to thecorresponding contacts through the interconnection.

The capacitive element and the aforementioned resistive module may bestacked up with each other first, and then being embedded into the firstdielectric layer together.

Otherwise, the resistive module can be fabricated by: providing asubstrate and forming a resistive thin film thereon. In addition, thesteps of fabricating the resistive module may further include: forming aplurality of electrodes on the substrate, wherein the resistive thinfilm is electrically connected with the electrodes; and, forming apassivation layer on the substrate to cover the electrodes and theresistive thin film.

According to an embodiment of the present invention, the firstelectronic component is a semiconductor chip or a wafer.

According to an embodiment of the present invention, the secondelectronic component is a semiconductor chip or a wafer.

Accordingly, since the interposer structure of the present inventiondoes not contain semiconductor substrate, therefore the interposerstructure is thinner and smaller in size. In addition, because of thecapacitive element is located closer to either the first electroniccomponent or the second electronic component, the efficiency is improvedwhen the capacitive element is served as a de-coupling capacitor.Furthermore, according to the method of fabricating packaging structureof the present invention, the capacitive element can be manufacturedindividually before being embedded into the first dielectric layer.Therefore, the fabricating method of packaging structure can beintegrated with the conventional process and thus has lower cost.

In order to make the aforementioned and other objects, features andadvantages of the present invention comprehensible, a preferredembodiment accompanied with figures are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic view of a conventional stacked circuit device.

FIG. 2 is a schematic view of another conventional stacked circuitdevice.

FIG. 3 is a schematic view showing a packaging structure according to anembodiment of the present invention.

FIG. 4 is a flow chart showing the steps of fabricating a packagingstructure according to an embodiment of the present invention.

FIGS. 5A to 5C are cross-sectional views schematically illustrating thesteps of fabricating a packaging structure according to an embodiment ofthe present invention.

FIGS. 6A to 6F are cross-sectional views schematically showing afabricating process of a capacitive element.

FIGS. 7A to 7C are cross-sectional views schematically showing afabricating process of the interposer structure shown in FIG. 5B.

FIG. 8 is a flow chart illustrating a fabricating method of a packagingstructure according to another embodiment of the present invention.

FIG. 9 is a cross-sectional view schematically illustrating the stepsS020′ shown in FIG. 8.

FIGS. 10A to 10B are cross-sectional views schematically showing afabricating process of the resistive module shown in FIG. 9.

FIG. 11 is a flow chart illustrating a fabricating method of a packagingstructure according to another embodiment of the present invention.

FIG. 12 is a cross-sectional view schematically showing the steps S020″shown in FIG. 11.

DESCRIPTION OF EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

Referring to FIG. 3, a cross sectional view showing a packagingstructure according to an embodiment of the present invention isillustrated. A packaging structure 300 includes an interposer structure310, a first electronic component 320 and a second electronic component330, wherein the first electronic component 320 and a second electroniccomponent 330 can be either semiconductor chip or wafer. The interposerstructure 310 includes a first dielectric layer 311, a plurality ofcontacts 312, a capacitive element 313, an inductive element 314 and aninterconnection 315. The contacts 312 are disposed on the upper surface311 a and lower surface 311 b of the first dielectric layer 311. Thecapacitive element 313 is embedded into the first dielectric layer 311.And, the capacitive element 313 comprises two conductive layers 313 aand a second dielectric layer 313 b located between the conductivelayers 313 a. The inductive element 314 and the interconnection 315 areembedded into the first dielectric layer 311. The capacitive element 313and the inductive element 314 are electrically connected to thecorresponding contacts 312 through the interconnection 315. The firstelectronic component 320 and the second electronic component 330 arerespectively disposed on the upper and lower sides of the interposerstructure 310 and electrically connected to the corresponding contacts312.

In the present embodiment, the permittivity of the first dielectriclayer 311 is smaller than that of the second dielectric layer 313 b.Since the permittivity of the second dielectric layer 313 b of thecapacitive element 313 is higher, a higher capacitance value of thecapacitive element 313 can be attained. On the other hand, since thepermittivity of the first dielectric layer 311 is lower, the parasiticcapacitance of the inductive element 314 is lower and thus has a betterQ-factor. When being as a decoupling capacitor, the efficiency of thecapacitive element 313 can be improved by arranging the capacitiveelement 313 near by the first electronic component 320 and the secondelectronic component 330, according to the necessity of the design.

In the present embodiment, the spiral-like inductive element 314 can bedisposed surrounding the capacitive element 313, resulting the highintegration density of the passive element of the interposer structure310, thus the interposer structure 310 is thinner and smaller in size.In addition, the capacitive element 313 further includes a barrier layer313 c, which is disposed between one of the conductive layers 313 a andthe second dielectric layer 313 b. The material of the barrier layer 313c includes titanium (Ti), platinum (Pt), or silver (Ag). The barrierlayer 313 c can prevent the conductive layers 313 a from reacting withthe second dielectric layer 313 b when fabricating the capacitiveelement 313. The material of the second dielectric layer 313 b locatedat the capacitive element 313 includes ceramic, such as theferroelectric materials of barium titanate (BaTiO3) or strontiumtitanate (SrTiO3); and the material of the first dielectric layer 311includes benzocyclobutene (BCB) or polyimide (PI).

Referring to FIG. 3, the interposer structure 310 further includes aresistive module 316, which is embedded into the first dielectric layer311 and stacked up with the capacitive element 313. According to therelative position shown in FIG. 3, the capacitive element 313 can bestacked up on the resistive module 316, and the resistive module 316 iselectrically connected to the corresponding contacts 312 through theinterconnection 315. The resistive module 316 includes a substrate 316a, which can be made of ceramic, and a resistive film 316 b. Theresistive film 316 b is disposed on the substrate 316 a and electricallyconnected to the interconnection 315. Moreover, the resistive module 316includes a plurality of electrodes 316 c and a passivation layer 316 d.The electrodes 316 c are disposed on the substrate 316 a and theresistive film 316 b is connected to the interconnection 315 via theelectrodes 316 c. The passivation layer 316 d is disposed on thesubstrate 316 a and covers the resistive film 316 b and the electrodes316 c.

It should be noted that even though the interposer structure 310 of theabove embodiment, comprises of the capacitive element 313, the inductiveelement 314 and resistive module 316 for an example. In anotherembodiment, the interposer structure 310 may only contain the capacitiveelement 313 for serving as de-coupling capacitors. Therefore, theefficiency of the capacitive element 313, which serves as a decouplingcapacitor, can be improved by arranging the capacitive element 313 nearby the first electronic component 320 and the second electroniccomponent 330, according to the necessity of the design.

The following is a detailed description of a fabricating method of apackaging structure according to an embodiment of the present invention.FIG. 4 is a flow chart showing the steps of fabricating the packagingstructure. FIGS. 5A to 5C are cross-sectional views schematicallyillustrating the steps of fabricating the packaging structure. Thefabricating method of the packaging structure of the present embodimentincludes the steps S010, S020 and S030. Referring to FIGS. 4 and 5A,first of all, the step S010 is carried out to form the capacitiveelement 313.

FIGS. 6A to 6F are cross-sectional views schematically showing afabricating process of the capacitive element shown in FIG. 5A. Thefabricating method of the capacitive element 313 includes the followingsub-steps. First, referring to FIG. 6A, a metal film M is provided.Next, referring to FIG. 6B, a barrier layer 313 c can be formed on themetal film M to prevent the reaction of the metal film M with thedielectric material D formed in the following steps and thus preservethe dielectric characteristic of the dielectric material D if the metalfilm M will react with the dielectric material D. Referring to FIG. 6C,a dielectric material D, such as a suspended ceramic slurry, is coatedon the metal film M, wherein the ceramic slurry can be prepared from thenanometer ferroelectric material powder by performing the sol-gelmethod. Then, referring to FIG. 6D, the manufacturing process of, forexample, a thermal treatment, such as annealing, is performed to thedielectric material D. Referring to FIG. 6E, an electrode layer E isformed on the dielectric material D to finish the basic manufacture ofthe capacitive element 313. After that, referring to the Fig. 6F, thefinished capacitive element 313 can be trimmed into a certain size.Referring to FIG. 6F, the trimmed capacitive element 313 comprises twoconductive layers 313 a, a second dielectric layer 313 b located amongthe conductive layers 313 a, and a barrier layer 313 c disposed betweenthe second dielectric layer 313 b and one of the conductive layers 313a.

Then, referring to FIGS. 4 and 5B, an interposer structure 310 is formedthrough the steps S020, wherein a first dielectric layer 311 is formedon a first electronic component 320 through the build-up process. Aninductive element 314 and an interconnection 315 are fabricated in thefirst dielectric layer 311. In addition, a plurality of contacts 312 areformed on the upper surface 311 a and lower surface 311 b of the firstdielectric layer 311. Furthermore, the capacitive element 313 isembedded into the first dielectric layer 311 during the fabrication ofthe inductive element 314 and the interconnection 315 to let thecapacitive element 313 and the inductive element 314 electricallyconnect to the corresponding contacts 312 through the interconnection315 respectively.

FIGS. 7A to 7C are cross-sectional views schematically showing afabricating process of the interposer structure 310 shown in FIG. 5B,which includes the following sub-steps. First, referring to FIG. 7A, aplurality of first sub-contacts 312 a, a first sub-dielectric layer 311c, and a first sub-interconnection 315 a are formed on the firstelectronic component 320, wherein the first electronic component 320 iselectrically connected to the first sub-interconnection 315 a throughthe first sub-contacts 312 a. The first sub-contacts 3 12 a are disposedbetween the first sub-dielectric layer 311 c and the first electroniccomponent 320 and the first sub-interconnection 315 a is disposed on andin the first sub-dielectric layer 311 c. (Not shown)

Next, referring to FIG. 7B, the capacitive element 313 is disposed ontothe first sub-dielectric layer 311 c. Then, an etching process isperformed on the capacitive element 313 to define the capacitor surfacearea.

As shown in FIG. 7C, a plurality of second sub-contacts 312 b, a secondsub-dielectric layer 311 d, a second sub-interconnection 315 b and ainductive element 314 are formed on the first sub-dielectric layer 311 cthrough the build-up process, wherein the capacitive element 313 and theinductive element 314 are embedded into the second sub-dielectric layer311 d. The second sub-contacts 312 b are disposed on the secondsub-dielectric layer 311 d. The second sub-interconnection 315 b areembedded into the second sub-dielectric layer 311 d and electricallyconnected to the first sub-interconnection 315 a. The firstsub-dielectric layer 311 c and the second sub-dielectric layer 311 dcompose a first dielectric layer 311. The first sub-interconnection 315a and the second sub-interconnection 315 b compose an interconnection315. The first sub-contacts 312 a and the second sub-contacts 312 bcompose the contacts 312. The capacitive element 313 and the inductiveelement 314 are electrically connected to the corresponding contacts 312through the interconnection 315 respectively. It should be noted thatthe permittivity of the first dielectric layer 311 can be smaller thanthat of the second dielectric layer 313 b of the capacitive element 313and the inductive element 314 may be disposed surrounding the capacitiveelement 313.

Then, referring to FIGS. 4 and 5C, step S030 is carried out to dispose asecond electronic component 330 on the first dielectric layer 311 andelectrically connect the second electronic component to thecorresponding contacts 312. To be more specific, the second electroniccomponent 330 is disposed on the second sub-dielectric layer 311 dthrough the flip chip bonding technology and electrically connected tothe second sub-contacts 312 b.

A fabricating method of a packaging structure of another embodiment ofthe present invention is illustrated in detail as follows. Referring toFIGS. 4, 8 and 9, wherein FIG. 8 is a flow chart illustrating afabricating method of a packaging structure according to anotherembodiment of the present invention, and FIG. 9 is a cross-sectionalview schematically illustrating the steps S020′ shown in FIG. 8. Thefabricating method of the packaging structure of the present embodimentincludes the steps S010′, S020′ and S030′, wherein the steps S010′ andS030′ are identical with the steps S010 and S030, thus the detail isomitted herein.

The difference between the present embodiment and the above embodimentof the packaging structure fabricating method is that: the presentembodiment further provides a resistive module 316 at the step S020′during the fabrication of the inductive element 314 and theinterconnection 315, and makes the resistive module 316 and thecapacitive element 313 stack up with each other in order to be embeddedinto the first dielectric layer 311, wherein the resistive module 316 iselectrically connected to the corresponding contacts 312 through theinterconnection 315. It should be noted that the above mentioned methodof stacking up the resistive module 316 with the capacitive element 313and to be embedded into the first dielectric layer 311, is performed byfirst to stack up the capacitive element 313 and the resistive module316 and then embedded them into the first dielectric layer 311.

FIGS. 10A to 10B are cross-sectional views schematically showing afabricating process of the resistive module shown in FIG. 9. Thefabricating process of the resistive module 316 includes the followingsub-steps. First, referring to FIG. 10A, a substrate 316 a is provided.Then, plural electrodes 316 c are formed on the substrate 316 a. Next,referring to FIG. 10B, a resistive thin film 316 b is formed on thesubstrate 316 a and electrically connected to the electrodes 316 c.Then, a passivation layer 316 d is formed on the substrate 316 a tocover the electrodes 316 c and the resistive thin film 316 b.Furthermore, according to needs, the substrate 316 a can be thinned outto make the thickness of the resistive module 316 complied with thedesign requirements after the above steps.

A fabricating method of a packaging structure of another embodiment ofthe present invention is illustrated in detail as follows. Referring toFIGS. 4, 11 and 12, FIG. 11 is a flow chart illustrating a fabricatingmethod of a packaging structure according to another embodiment of thepresent invention. And the FIG. 12 is a cross-sectional viewschematically illustrating the steps S020″ shown in FIG. 11. Thefabricating method of the packaging structure of the present embodimentincludes the steps S010″, S020″ and S030″, wherein the steps S010″ andS030″ are identical with the steps S010 and S030, thus the detail isomitted herein.

The difference between the present embodiment and the above embodimentof the packaging structure fabricating method is that: the presentembodiment of the packaging structure only embeds one passive element,the capacitive element 313, into the first dielectric layer 311 at thestep S020″.

In summary, the packaging structure and the fabricating method thereofhave at least the following advantages:

-   -   1. Since the interposer structure of the present invention does        not contain semiconductor substrates, the interposer structure        is thinner and smaller in size.    -   2. Because the capacitive element is located closer to either        the first electronic component or the second electronic        component, the efficiency is improved when the capacitive        element is served as a de-coupling capacitor.    -   3. The permittivity of the second dielectric layer is higher to        attain a higher capacitance. On the other hand, since the        permittivity of the first dielectric layer is lower, the        parasitic capacitance value of the inductive element is lower        and thus has a better Q-factor.    -   4. The spiral-like inductive element can be disposed surrounding        the capacitive element to achieve a high integration density of        the passive element of the interposer structure. In addition,        the thickness and the size of the interposer structure can be        reduced.    -   5. The capacitive element can be manufactured individually        first, and then be embedded into the first dielectric layer.        Therefore, the fabricating method of the present invention can        be integrated with the conventional process to decrease the        manufacturing cost.    -   6. The capacitive element and the resistive module can be        manufactured individually first, and then be stacked to each        other and embedded into the first dielectric layer. Therefore,        the fabricating method of the present invention can be        integrated with the conventional process to decrease the        manufacturing cost.

The present invention has been disclosed above in the preferredembodiments, but is not limited to those. It is known to persons skilledin the art that some modifications and innovations may be made withoutdeparting from the spirit and scope of the present invention. Therefore,the scope of the present invention should be defined by the followingclaims.

What is claimed is:
 1. A packaging structure, comprising: an interposerstructure, including: a first dielectric layer; a plurality of contacts,which are disposed on the upper and lower surfaces of the firstdielectric layer; a capacitive element, which is embedded into the firstdielectric layer and the capacitive element comprises two conductivelayers and a second dielectric layer among them; an interconnection,which is embedded into the first dielectric layer and the capacitiveelement electrically connects to the corresponding contacts through theinterconnection; and a first electronic component and a secondelectronic component, which are electrically connected to thecorresponding contacts and respectively disposed on the upper and lowersides of the interposer structure.
 2. The packaging structure asdescribed in claim 1, wherein the permittivity of the first dielectriclayer is smaller than that of the second dielectric layer.
 3. Thepackaging structure as described in claim 1, further comprising aninductive element embedded into the first dielectric layer.
 4. Thepackaging structure as described in claim 3, wherein the inductiveelement is disposed surrounding the capacitive element.
 5. The packagingstructure as described in claim 1, wherein the capacitive elementfurther includes a barrier layer, which is disposed between one of theconductive layers and the second dielectric layer.
 6. The packagingstructure as described in claim 5, wherein the material of the barrierlayer includes titanium (Ti), platinum (Pt), or silver (Ag).
 7. Thepackaging structure as described in claim 1, wherein the material of thesecond dielectric layer includes ceramic.
 8. The packaging structure asdescribed in claim 7, wherein the material of the second dielectriclayer includes barium titanate (BaTiO3) or strontium titanate (SrTiO3).9. The packaging structure as described in claim 1, wherein the materialof the first dielectric layer includes benzocyclobutene (BCB) orpolyimide (PI).
 10. The packaging structure as described in claim 1,wherein the interposer structure further includes a resistive module,which is embedded into the first dielectric layer and stacked up withthe capacitive element, and the resistive module is electricallyconnected to the corresponding contacts through the interconnection. 11.The packaging structure as described in claim 10, wherein the resistivemodule comprises: a substrate; and a resistive thin film, which isdisposed on the substrate and electrically connects to theinterconnection.
 12. The packaging structure as described in claim 11,wherein the resistive module further comprises: a plurality ofelectrodes, which are disposed on the substrate and the resistive thinfilm is connected to the interconnection through the electrodes; and apassivation layer, which is disposed on the substrate and covers theresistive thin film and the electrodes.
 13. The packaging structure asdescribed in claim 11, wherein the material of the substrate is ceramic.14. The packaging structure as described in claim 1, wherein the firstelectronic component is a semiconductor chip or a wafer.
 15. Thepackaging structure as described in claim 1, wherein the secondelectronic component is a semiconductor chip or a wafer.
 16. Afabricating method of packaging structure, comprising: forming acapacitive element; forming a first dielectric layer on a firstelectronic component by performing a build-up process, forming aninterconnection in the first dielectric layer, and forming a pluralityof contacts on the upper and lower surfaces of the first dielectriclayer, wherein the capacitive element is embedded in the firstdielectric layer during the fabrication of the interconnection and thecapacitive element is electrically connected to the correspondingcontacts through the interconnection; and disposing a second electroniccomponent on the first dielectric layer, wherein the second electroniccomponent is electrically connected to the corresponding contacts. 17.The fabricating method of the packaging structure as described in claim16, wherein the capacitive element comprises two conductive layers and asecond dielectric layer located among them, in which the permittivity ofthe first dielectric layer is smaller than that of the second dielectriclayer.
 18. The fabricating method of the packaging structure asdescribed in claim 16, further comprising forming an inductive elementat the same time of fabricating the interconnection and the inductiveelement is electrically connected to the corresponding contacts throughthe interconnection.
 19. The fabricating method of the packagingstructure as described in claim 18, wherein the inductive element isdisposed surrounding the capacitive element.
 20. The fabricating methodof the packaging structure as described in claim 16, wherein the stepsof forming the capacitive element includes: providing a metal film;coating a dielectric material on the metal film; and forming anelectrode layer on the dielectric material.
 21. The fabricating methodof the packaging structure as described in claim 20, wherein thedielectric material includes ceramic slurry.
 22. The fabricating methodof the packaging structure as described in claim 20, further comprisingperforming a thermal treatment process to the dielectric material aftercoating the same.
 23. The fabricating method of the packaging structureas described in claim 20, further comprising forming a barrier layer onthe metal film before coating the dielectric material.
 24. Thefabricating method of the packaging structure as described in claim 20,wherein the finished capacitive element is trimmed into a certain sizeafter the electrode layer is formed.
 25. The fabricating method of thepackaging structure as described in claim 20, further comprisingperforming an etching process to the capacitive element to define thesurface area thereof after the capacitive element is embedded into thefirst dielectric layer.
 26. The fabricating method of the packagingstructure as described in claim 16, further comprising providing aresistive module at the same time of fabricating the interconnection,and making the resistive module and the capacitive element stacked upwith each other and to be embedded into the first dielectric layer,wherein the resistive module is electrically connected to thecorresponding contacts through the interconnection.
 27. The fabricatingmethod of the packaging structure as described in claim 26, wherein thecapacitive element and the resistive module are stacked up with eachother first, and then being embedded into the first dielectric layertogether.
 28. The fabricating method of the packaging structure asdescribed in claim 26, wherein the steps of fabricating the resistivemodule includes: providing a substrate; and forming a resistive thinfilm on the substrate.
 29. The fabricating method of the packagingstructure as described in claim 28, wherein the steps of fabricating theresistive module further includes: forming a plurality of electrodes onthe substrate, wherein the resistive thin film is electrically connectedwith the electrodes; and forming a passivation layer on the substrate tocover the electrodes and the resistive thin film.
 30. The fabricatingmethod of the packaging structure as described in claim 16, wherein thefirst electronic component is a semiconductor chip or a wafer.
 31. Thefabricating method of the packaging structure as described in claim 16,wherein the second electronic component is a semiconductor chip or awafer.